Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner

S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima
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引用次数: 2

Abstract

Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.
采用大马士革栅极工艺和拉伸衬垫的窄化 NMOSFET 中的应力增强技术
通过三维应力模拟和演示,研究了 nFET 沟道宽度上的顶切拉伸 SiN 应力衬垫和大马士革栅极(栅极-最后)工艺组合所引起的局部沟道应力行为。研究发现,去除假栅极会增强栅极长度上的高拉伸沟道应力,尤其是在 STI 旁的沟道边缘。因此,具有窄沟道宽度的大马士革栅 nFET 的驱动能力得到了增强。通过大马士革栅极技术的应力增强效应,在 Ioff = 100 nA/um、Vdd = 1.0 V 和 0.3 um 沟道宽度条件下实现了 1430 uA/um 的高驱动电流。
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