S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima
{"title":"Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner","authors":"S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima","doi":"10.1109/VTSA.2009.5159273","DOIUrl":null,"url":null,"abstract":"Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.