{"title":"Correction of Self-Heating for HCI Lifetime Prediction","authors":"J. Roux, X. Federspiel, D. Roy, P. Abramowitz","doi":"10.1109/RELPHY.2007.369905","DOIUrl":null,"url":null,"abstract":"Self-heating (SH) effects, observed during the development of SOI technology for high performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). The integration of buried oxide, with low thermal conductivity, enhances self-heating (SH) in MOS transistor devices submitted to DC HCI stress, and leads to potential erroneous HCI lifetime prediction. In this paper, the authors propose a new methodology for the lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements, for different transistor widths (W). Then, the degradation part due to SH is removed enabling accurate HCI lifetime prediction.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2007.369905","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Self-heating (SH) effects, observed during the development of SOI technology for high performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). The integration of buried oxide, with low thermal conductivity, enhances self-heating (SH) in MOS transistor devices submitted to DC HCI stress, and leads to potential erroneous HCI lifetime prediction. In this paper, the authors propose a new methodology for the lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements, for different transistor widths (W). Then, the degradation part due to SH is removed enabling accurate HCI lifetime prediction.