Efficient built-in self test of regular logic characterization vehicles

Abstract

Fast and efficient analysis of test chips is crucial for effective yield learning. Prior work proposed the Carnegie-Mellon logic characterization vehicle (CM-LCV) as an improved test chip for yield learning. The highly regular nature of the CM-LCV test chip is particularly appealing for BIST; the current work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design. Furthermore, all of these properties are achieved with a minimal hardware overhead.