Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier

Abstract

The arithmetic operations namely addition and multiplication play a vital role in digital signal processing applications such as filtering, and equalization. In this work, we developed such a filtering application using hybrid adder, modified Booth multiplier together with multiple-and-accumulate (MAC) unit. The hybrid adder incorporates two or three prevailing adder scheme, leads to significant improvement in speed of operation and lower power consumption. Similarly for multiplication, we adopted the modified Booth multiplier, where a radix-4 encoding scheme is used. The designed adder and multiplier are utilized to design a MAC unit that performs multiplication and addition together. Using the developed MAC unit a digital finite impulse response (FIR) filter is designed with 8-MAC units. The performance metrics such as delay and power consumption are measured using Cadence Virtuoso with 180 nm, 90 nm and 45 nm TSMC technology libraries.