A Production Parylene Coating Process for Hybrid Microcircuits

V. Kale, T. Riley
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引用次数: 22

Abstract

Application of Parylene for protecting microelectronic circuits from loose particles and external environment has been visualized for many years. With a joint effort by NASA and TMD, a process has now been qualified to perform Parylene deposition on hybrid circuits on a production basis, for the Centaur inertial guidance computer. The Parylene coating process developed during this program consists of a) obtaining a hybrid cover with a hole in it, b) sealing of the circuit with a hole in the cover, c) Parylene coating through the hole with the external leads protected from Parylene by appropriate fixturing, and d) sealing of the hole by soldering a pretinned Kovax tab. Development of the above process required optimization of the Parylene coater parameters to obtain a uniform consistent coating which could offer adequate protection to the circuits, fixture design for packages of various types, determination of the size of the deposition hole, the amount of dimer charge per run, a process to hermetically seal the deposition holes and establishment of quality control techniques or acceptance criteria for the deposited film. Several experimental runs were made on test circuits as well as actual production circuits to determine the effect of Parylene coating on active components, thin film resistors, and wire bonds under various conditions. Tests were also made to determine if Parylene indeed protected circuits from loose particles and external environment. After these experiments, Parylene coating acceptance standards were established and a long and rigorous qualification program was completed in order to prove the feasibility of this process. The results of the qualification program will be reported in a future publication. It is concluded that Parylene offers excellent protection against loose particles and a degree of protection from some environmental conditions. It is expected that the fraction of hybrids being coated with Parylene will continue to increase in the microelectronic industry.
一种用于混合微电路的聚对二甲苯涂层生产工艺
聚对二甲苯在保护微电子电路免受松散颗粒和外界环境影响方面的应用已经有多年的历史。在NASA和TMD的共同努力下,一种工艺现在已经合格,可以在半人马惯性制导计算机的混合电路上进行聚对二甲苯沉积。在此计划中开发的聚对二甲苯涂层工艺包括:a)获得带有孔的混合盖板,b)在盖板上有孔的电路密封,c)通过孔的聚对二甲苯涂层,并通过适当的固定装置保护外部引线不受聚对二甲苯的影响,d)通过焊接预镀的Kovax标签密封孔。上述工艺的发展需要对聚对二甲苯涂层机参数进行优化,以获得均匀一致的涂层,从而为电路提供足够的保护,为各种类型的封装设计夹具,确定沉积孔的大小,每次运行的二聚体电荷量,密封沉积孔的过程以及建立沉积膜的质量控制技术或验收标准。在测试电路和实际生产电路上进行了几次实验,以确定在各种条件下,聚对二甲苯涂层对有源元件、薄膜电阻器和导线键合的影响。还进行了测试,以确定聚二甲苯是否确实保护电路免受松散颗粒和外部环境的影响。经过这些实验,建立了聚对二甲苯涂层的验收标准,并完成了漫长而严格的鉴定程序,以证明该工艺的可行性。资格程序的结果将在未来的出版物中报告。结果表明,聚对二甲苯对松散颗粒有很好的防护作用,对某些环境条件也有一定程度的防护作用。预计在微电子工业中,用聚对二甲苯涂层的混合材料的比例将继续增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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