Hybrid Protective Device for MOS-LSI Chips

Abstract

In this paper, several structures that can be used to protect MOS-LSl chips against electrostatic discharges (ESD) are examined experimentally to determine some of the possible specification tradeoffs that result in improved overall performance. It is shown that by using structures able to withstand larger energy discharges at the expense of their voltage-clamping characteristics, higher overvoltages can be handled. Additional protection is possible by incorporating a spark-gap device on the chip-carrying module. Conditions under which this hybrid combination is effective are ex- amined.