Chip-to-Chip/Wafer Three-Dimensional Integration of 2.5 mm-sized Neuron and Memory Chips by Via-Last Approach

Abstract

A low thermal budget (≤ 250 °C) chip-to-chip and chip-to-wafer three-dimensional (3D) integration of application-specific smaller artificial intelligence (AI) chips (2.5 mm × 2.5 mm) with 6 level metal (M#) layers were carried out by using TSV (Through – Si - Via) - last method. Several back-end-of-line processes were carefully optimized, such as multi-die thinning, M1 revealing, protection of revealed M1 during TSV metallization, die-level Cu-chemical mechanical polishing for re-distribution layer formation, and μ-bumping were carefully optimized. The diode parameter evaluation for the chips before and after 3D-integration revealed the successful fabrication of AI module for specific applications.