Challenges of III–V materials in advanced CMOS logic

Abstract

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N_D=5×10¹⁹ cm^-3, ρ_c= 6Ω.μm² and Dit = 4×10¹² eV^-1 cm^-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.