M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. Pagès
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引用次数: 7
Abstract
In this paper, a new concept of lateral DMOSFET for medium voltage (<100 Volts) Smart Power Integrated Circuits is proposed. This structure called LUDMOSFET features a reduced specific on-resistance and enhanced breakdown voltage. For example, for a breakdown voltage of 50 V, the specific on-resistance is 1.2 m/spl Omega/.cm/sup 2/ in the conventional LDMOSFET, 0.8 m/spl Omega/.cm/sup 2/ in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 m/spl Omega/.cm/sup 2/ in the LUDMOS with polysilicon (i.e. 50 percent reduction).