Numerical Characterisation of Electronic Packaging Solutions based on Hidden Dies

Abstract

Innovative electronic portable products can be characterised by increasing signal frequencies and the demand on higher density of functions, which requires more space, for active components as well as for passives. One way to meet these requirements is a three-dimensional integration of components. The authors follow a so-called “chip in polymer” approach, which allows an extremely dense integration and very short interconnects. Thinned Si-components are embedded directly into the printed circuit boards, and the interconnects are realised by laser drilling and galvanic metallisation. In order to achieve high functionality and reliability and to minimise the number of later redesign loops, thermal and thermo-mechanical reliability aspects are taken into account already from the initial design phase. For this purpose, numerical studies by means of finite element (FE) analyses are very efficient to check the desired properties. The authors’ approach for a package design, containing different types of test structures and ICs, is outlined. First, FE calculations were carried out in order to study the thermal performance. The number, positions, and dimensions of thermal vias were investigated in detail, and their influence on leading heat off could be evaluated. Beside this, the fraction of copper in the top metallisation layer of the package was taken into account. In order to reduce the number of necessary real parts and the effort for the test procedures, a special test board was designed with different versions of interconnects between the hidden dies and the ambient.