Package Level Warpage Simulation of Fan-out Wafer Level Package (FOWLP) Considering Viscoelastic Material Properties

Abstract

In this paper, the package level warpage of different package sizes of mold-first and redistribution layer-first (RDL-first) Fan-out wafer level package (FOWLP) with single chip was studied by finite element simulation considering viscoelastic material properties of epoxy molding compound (EMC), dielectric and underfill. Package level warpage at high temperature is underestimated for mold-first/RDL-first FOWLP with elastic material properties of EMC, dielectric and underfill. The package warpage changing before and after reflow can be captured with viscoelastic material properties. Package level warpage increases with the package size. Warpage of RDL-first FOWLP is larger than that of mold-first FOWLP with same package thickness of $200 \mu \mathrm{m}$ which is caused by the stiffness reduction due to thinner silicon chip and additional CTE mismatch of underfill/micro-bump layer. Package level warpage of mold-first and RDL-first FOWLP reduces with increasing of package thickness. Thickness of mold-first and RDL-first FOWLP was determined in order to meet the target of within $\pm 100 \mu \mathrm{m}$ warpage during reflow process required by the JEITA ED7306 standard of $250 \mu \mathrm{m}$ diameter solder joint with $400 \mu \mathrm{m}$ pitch.