Semi-empirical interconnect resistance model for advanced technology nodes: A model apt for materials selection based upon test line resistance measurements

Abstract

A semi-empirical interconnect resistance model apt for fitting wire resistance data is presented. The model combines grain boundary and sidewall scattering effects with the impact of Line Edge Roughness (LER). After calibration onto experimental meander-fork structure resistance measurements, extrapolation of the model to future technology nodes reveals that for ultra-narrow line widths a better LER control will be imperative. The model is also intended for inclusion of more accurate, geometry dependent interconnect and via resistance estimators in higher abstraction level simulators, enabling a more realistic assessment of the impact of BEOL parasitics on circuit delay and power at advanced technology nodes.