Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance

L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans
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引用次数: 1

Abstract

This paper overviews integration challenges of low-VT gate-first CMOS featuring one metal gate electrode and one host dielectric with Al2O3 and La2O3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low VT enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.
单金属双介电(SMDD)栅极优先CMOS集成,实现低VT和高性能
本文概述了低vt门优先CMOS的集成挑战,该CMOS具有一个金属栅极和一个主介质,分别用于pMOS和nMOS的Al2O3和La2O3帽介电体。在处理简单性以及设备性能和可靠性方面,比较了所采用的低EOT低VT使能技术的优缺点。最新的最先进的SMDD器件结果报告。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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