L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans
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引用次数: 1
Abstract
This paper overviews integration challenges of low-VT gate-first CMOS featuring one metal gate electrode and one host dielectric with Al2O3 and La2O3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low VT enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.
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