SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

M. Collantes, Zahra Ghodsi, S. Garg
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引用次数: 6

Abstract

We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network’s computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU’s area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.
SafeTPU:一种可验证的深度神经网络安全硬件加速器
我们提出了Safe-TPU,这是一个用于在被木马或故障注入攻击破坏的不可信硬件中安全计算深度神经网络(dnn)的框架。这项工作利用了交互式证明(IP)系统的先前进展,用于在运行时验证神经网络计算的正确性,并做出了三个新的贡献:(1)我们提出了一个基于交互式证明的木马弹性DNN硬件加速器;(2)我们引入了新的协议增强功能,大大减少了生成证明所需的空间和时间;(3)我们提出了一种具有高并行性和重用已经部署在基线DNN加速器中的现有资源的Safe-TPU实现。在FPGA上对Safe-TPU进行了原型设计,并对其安全性进行了分析。实验表明,Safe-TPU的面积开销比基线DNN加速器小(28%),比最先进的速度快3.15倍,同时,Safe-TPU保证以高概率捕获任何不正确的计算。
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