Interface Trap Effects in the Design of a 4H-SiC MOSFET for Low Voltage Applications

Abstract

The current-voltage characteristics of a 4H-SiC MOSFET dimensioned for a breakdown voltage of 650 V are investigated by means of a numerical simulation study that takes into account the defect state distribution at the oxide-semiconductor interface in the channel region. The modelling analysis reveals that, for these low-voltage devices, the channel resistance component plays a key role in determining the MOSFET specific ON-state resistance (RON) under different voltage biases and temperatures. The RON value is in the order of a few mΩ×cm2.