Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node

Abstract

ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of Vgox, and Vt1, and It2 of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis discussed.