Reaction barrier formation of W/poly-Si gate by NH/sub 3/ rapid thermal annealing applicable to 0.15 /spl mu/m CMOS devices

Abstract

We found that an NH/sub 3/ rapid thermal annealing of Wi/poly-Si gate above 750/spl deg/C resulted in the formation of a highly reliable in-situ barrier layer and low resistivity W, simultaneously. This barrier layer kept the Wi/poly-Si gate stable up to the elevated temperature of 1000/spl deg/C. Ammonia treated W/poly-Si gate showed a narrow distribution of sheet resistance at a line width of 0.15 /spl mu/m after the post annealing at 900/spl deg/C for 30 min. This W/poly-Si gate was acceptable to apply to 0.15 /spl mu/m CMOS devices without deposition of a barrier layer.