III–V-based low power CMOS devices on Si platform

Abstract

CMOS utilizing high mobility III–V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunnel FETs (TFETs) using III–V channel materials are regarded as one of the most promising steep slope devices for the ultra-low power applications. In this presentation, we address the critical issues for realizing III–V MOSFETs and TFETs on the Si CMOS platform. Viable technologies of MOS channel, gate stack, source/drain and tunnel junction formation are introduced for satisfying the device requirements. The electrical properties of ultrathin body InAs MOSFETs, InGaAs/Ge CMOS, InAs/GaSb CMOS, InGaAs TFETs and InGaAs/GaAsSb TFETs are presented.