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2017 IEEE International Conference on IC Design and Technology (ICICDT)最新文献

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Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies 先进FD-SOI CMOS技术中用于薄硅ESD保护的门控二极管- bimos
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993509
L. D. Conti, T. Bedecarrats, M. Vinet, S. Cristoloveanu, P. Galy
{"title":"Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies","authors":"L. D. Conti, T. Bedecarrats, M. Vinet, S. Cristoloveanu, P. Galy","doi":"10.1109/ICICDT.2017.7993509","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993509","url":null,"abstract":"This paper presents a new device named the Gated Diode merged BIMOS (GDBIMOS) which is fabricated using the 28nm UTBB FD-SOI high-k metal gate CMOS technology. It is highly reconfigurable and topologically robust for ESD protection. The suitable ESD window is achieved thanks to doping adjustment and to different possible gate connections.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114179468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
III–V-based low power CMOS devices on Si platform 基于Si平台的低功耗CMOS器件
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993497
S. Takagi, D. Ahn, T. Gotow, M. Noguchi, K. Nishi, S. Kim, M. Yokoyama, C. Chang, S. Yoon, C. Yokoyama, M. Takenaka
{"title":"III–V-based low power CMOS devices on Si platform","authors":"S. Takagi, D. Ahn, T. Gotow, M. Noguchi, K. Nishi, S. Kim, M. Yokoyama, C. Chang, S. Yoon, C. Yokoyama, M. Takenaka","doi":"10.1109/ICICDT.2017.7993497","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993497","url":null,"abstract":"CMOS utilizing high mobility III–V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunnel FETs (TFETs) using III–V channel materials are regarded as one of the most promising steep slope devices for the ultra-low power applications. In this presentation, we address the critical issues for realizing III–V MOSFETs and TFETs on the Si CMOS platform. Viable technologies of MOS channel, gate stack, source/drain and tunnel junction formation are introduced for satisfying the device requirements. The electrical properties of ultrathin body InAs MOSFETs, InGaAs/Ge CMOS, InAs/GaSb CMOS, InGaAs TFETs and InGaAs/GaAsSb TFETs are presented.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive SOTB(薄埋氧化物硅):物联网和汽车领域的摩尔技术
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993512
T. Hasegawa, Yoshiki Yamamoto, H. Makiyama, H. Shinkawata, S. Kamohara, Y. Yamaguchi
{"title":"SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive","authors":"T. Hasegawa, Yoshiki Yamamoto, H. Makiyama, H. Shinkawata, S. Kamohara, Y. Yamaguchi","doi":"10.1109/ICICDT.2017.7993512","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993512","url":null,"abstract":"Ultra low power performance is indispensable for Micro Controller Unit (MCU) used as wireless sensor and communication nodes which needs battery maintenance free and energy harvesting operation in the Internet of things (IoT) era. The Silicon on Thin Buried Oxide (SOTB) is one of the most suitable CMOS technology for ultra low power MCU because of its small variability and back bias controllability. This paper describes the mechanism of ultra low power performance of SOTB, performance demonstration of transistor, SRAM and MCU test chip, and what SOTB will realize for IoT and Automotive. SOTB will have less than 1/10 of power efficiency by low leakage current at standby mode and low current consumption at operation mode which today's technology cannot realize.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Microstructure and ferroelectricity of barium titanate thin films on Si for integrated photonics 集成光子学用钛酸钡硅薄膜的微观结构和铁电性
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993501
Kristy J. Kormondy, A. Demkov, Y. Popoff, M. Sousa, F. Eltes, D. Caimi, C. Marchiori, J. Fompeyrine, S. Abel
{"title":"Microstructure and ferroelectricity of barium titanate thin films on Si for integrated photonics","authors":"Kristy J. Kormondy, A. Demkov, Y. Popoff, M. Sousa, F. Eltes, D. Caimi, C. Marchiori, J. Fompeyrine, S. Abel","doi":"10.1109/ICICDT.2017.7993501","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993501","url":null,"abstract":"Significant progress has been made in integrating novel materials into silicon photonic structures to extend the functionality of photonic circuits. One of these promising optical materials, BaTiO3 (BTO), exhibits a large Pockels coefficient as required for high-speed light modulators. Here, we employ several deposition methods such as molecular beam epitaxy and chemical vapor deposition to realize BTO thin films with different morphology and crystalline structure. By identifying the key structural predictors of electro-optic response in BTO/Si, we provide a roadmap to fully exploit the linear electro-optic effect in novel hybrid oxide/semiconductor nanophotonic devices.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A resistance model of integrated octagonal-shaped Hall sensor using JFET compact model 基于JFET紧凑模型的集成八角形霍尔传感器电阻模型
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993510
Milos Skalsky, S. Banas, V. Panko
{"title":"A resistance model of integrated octagonal-shaped Hall sensor using JFET compact model","authors":"Milos Skalsky, S. Banas, V. Panko","doi":"10.1109/ICICDT.2017.7993510","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993510","url":null,"abstract":"This paper presents a resistance model of integrated octagonal-shaped Hall sensor device. The nonlinear voltage dependent, temperature and parasitic junction (leakage & capacitance) effects are modeled using JFET compact model. The model topology consists of eight nonlinear resistor models with two types of resistance. This approach reduces the number of model parameters with sustaining high model accuracy and reduces the modeling time significantly. The JFET compact model is available in many commercial SPICE simulators, e.g. Eldo, Spectre or Hspice.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133283407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor FDSOI高k金属栅极晶体管原子层沉积低k间隔层的表征
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993500
D. Triyoso, G. R. Mulfinger, K. Hempel, H. Tao, F. Koehler, L. Kang, A. Kumar, T. McArdle, J. Holt, A. Child, S. Straub, F. Ludwig, Z. Chen, J. Kluth, R. Carter
{"title":"Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor","authors":"D. Triyoso, G. R. Mulfinger, K. Hempel, H. Tao, F. Koehler, L. Kang, A. Kumar, T. McArdle, J. Holt, A. Child, S. Straub, F. Ludwig, Z. Chen, J. Kluth, R. Carter","doi":"10.1109/ICICDT.2017.7993500","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993500","url":null,"abstract":"FDSOI is one of the alternative device architectures chosen to extend CMOS scaling for high-k metal gate. FDSOI is ideal for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). One of the challenges in FDSOI integration is to obtain a low gate to source drain capacitance (overlap capacitance or DC capacitance). To enable this, low k spacer material is needed. In this study we compared two ALD low-k spacer materials namely SiOCN and SiBCN against the conventional SiN spacer. Material characterization reveals SiOCN has lower etch rate than SiBCN. Both materials have good thermal stability. Transistors with SiOCN and SiBCN spacers were formed. Implementation of low-k spacer does not have significant impact on VT variability and oxygen ingress. Transistors with SiOCN and SiBCN spacer exhibited lower DC and AC capacitance without transistor resistance degradation.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130967000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power fast wakeup flash memory system for embedded SOCs 一种用于嵌入式soc的低功耗快速唤醒闪存系统
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993516
Karthik Ramanan, Jacob Williams
{"title":"A low power fast wakeup flash memory system for embedded SOCs","authors":"Karthik Ramanan, Jacob Williams","doi":"10.1109/ICICDT.2017.7993516","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993516","url":null,"abstract":"This paper describes a system level approach to achieve a flash memory system that would consume very little current (less than a 1µA) in standby mode and would wake up fast (∼1µs) for a random-access read operation. The paper mainly focuses how analog circuits and other flash memory components can be partitioned to achieve these specifications. In addition, design considerations for various circuits have also been illustrated.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low power Adiabatic Logic based on 2PC2AL 基于2PC2AL的低功耗绝热逻辑
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993517
Mei Han, Yasuhiro Takahashi, T. Sekine
{"title":"Low power Adiabatic Logic based on 2PC2AL","authors":"Mei Han, Yasuhiro Takahashi, T. Sekine","doi":"10.1109/ICICDT.2017.7993517","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993517","url":null,"abstract":"This paper presents a new adiabatic circuit based on the 2-Phase Clocked CMOS Adiabatic Logic (2PC2AL). By adding two logic switches between the power supply and charging-discharging transistor, it can prevent the floating of the nodes and avoid unnecessary energy loss. In this paper, we apply the proposed adiabatic logic circuit to a 4×4-bit multiplier in the LTspice by using a 0.18 µm standard CMOS process. The simulation results show that the function of circuits can be realized and the power consumption can be reduced greatly compared to the CMOS circuit when the frequency ranges from 100 Hz to 100 MHz.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129668028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications FDSOI vs FinFET:超低功耗和物联网应用的差异化器件特性
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993513
O. Weber
{"title":"FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications","authors":"O. Weber","doi":"10.1109/ICICDT.2017.7993513","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993513","url":null,"abstract":"This paper reviews the main differentiating features of planar FDSOI devices vs planar bulk and 3D FinFETs for ultra-low power and IoT (Internet of Things) applications. The interest of using back-bias, the specific FDSOI device/design feature, to maximize the performance/power efficiency, to mitigate the process variability and to suppress the leakage is highlighted in this paper. Low parasitic gate capacitance, low VT mismatch associated with its undoped channel, and low gate resistance linked to the gate-first integration also bring some competitive advantages to FDSOI over FinFETs for Analog and RF devices.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"66 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116581531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Statistical circuit performance dependency analysis via sparse relevance kernel machine 基于稀疏相关核机的统计电路性能相关性分析
2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI: 10.1109/ICICDT.2017.7993507
H. Lin, A. Khan, Peng Li
{"title":"Statistical circuit performance dependency analysis via sparse relevance kernel machine","authors":"H. Lin, A. Khan, Peng Li","doi":"10.1109/ICICDT.2017.7993507","DOIUrl":"https://doi.org/10.1109/ICICDT.2017.7993507","url":null,"abstract":"Design optimization, verification, and failure diagnosis of analog and mixed-signal (AMS) circuits requires accurate models that can reliably capture complex dependencies of circuit performances on essential circuit and process parameters. We present a novel Bayesian learning technique, namely sparse relevance kernel machine (SRKM), for characterizing analog circuits with sparse statistical regression models. SRKM produces more reliable classification models learned from simulation data with a limited number of samples but a large number of parameters, and also computes a probabilistically inferred weighting factor quantifying the criticality of each parameter as part of the overall learning framework. As a result, it offers a powerful tool to enable variability modeling, failure diagnosis, and test development. The effectiveness of SRKM is demonstrated in an example of building a statistical variability model for analyzing the thermal shutdown feature of a data communication AMS system for automotive applications.","PeriodicalId":382735,"journal":{"name":"2017 IEEE International Conference on IC Design and Technology (ICICDT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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