Wafer level 3D system integration based on silicon interposers with through silicon vias

Abstract

This paper presents a detailed description of the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their subsequent assembly treatment. The electrical performance and characterization of the TSVs is also discussed. The interposers are created at 200 mm or 300 mm silicon wafers. The fabrication processes include deep reactive ion etching, TSV side wall isolation, PVD seed layer deposition, TSV filling by copper electroplating, wafer front side redistribution, temporary wafer bonding, wafer thinning by mechanical grinding, CMP, silicon dry etching, PECVD, silicon oxide dry etching and wafer backside redistribution. Depending on the final device application, after backside processing a component assembly is done directly at the interposer backside. In other cases, the interposer wafers are either released from the carrier wafers or transfer bonded so that their front side can be accessed again and the component assembly can be done. Finally, the assembled interposers can be release from their carrier wafers and singulated or run into further processes like molding or hermetic sealing by wafer to wafer bonding using suitable capwafers. In the following sections, important technological aspects of interposer fabrication and assembly as well as results from electrical characterizations will be presented. Detailed discussion of produced evaluation devices will explain and outline the versatility of the silicon interposer approach to be a flexible base technology for different application scenarios.