Electrical results of vertical Si N-Tunnel FETs

Abstract

This paper reports on the process integration of vertical Tunnel FETs (TFETs) and analyzes the impact of process and geometrical parameters on the device performance. The gate-source overlap is shown to be a critical parameter, especially when the overlap is marginal. The study also suggests that a high interface trap density is at the origin of the poor onset characteristic of the vertical TFET and that improvement in passivating the surface of the vertical nanowires should be beneficial.