Channel and near channel defects characterization in vertical InxGa1-xAs high mobility channels for future 3D NAND memory

Abstract

In this paper, we present a first characterization of the charge trapping in vertical 3D SONOS with InxGa1-xAs channel using IV hysteresis and RTN measurements. We show that III-V devices have a high density of border traps leading to an important variability of its electrical parameters. Finally, individual trap analysis show that the III-V devices also possess traps in the channel region and their behavior are similar to the one measured in standard silicon technology.