R. Jerome, I. Post, T.G. Travnicek, G.M. Wodek, K.E. Huffstater, D.R. Williams
{"title":"ACUTE: a high performance analog complementary polysilicon emitter bipolar technology utilizing SOI/trench full dielectric isolation","authors":"R. Jerome, I. Post, T.G. Travnicek, G.M. Wodek, K.E. Huffstater, D.R. Williams","doi":"10.1109/SOI.1993.344573","DOIUrl":null,"url":null,"abstract":"The advantages of using full dielectric isolation, in the form of SOI substrates and trench isolation, are well known, namely the reduction of substrate parasitic currents due to high voltage, high temperature or harsh radiation environments. Moreover, high voltage analog bipolar transistors can also benefit from full dielectric isolation in terms of limiting substrate capacitance and providing the means to achieve well matched, densely packed transistors. A high voltage analog SOI/trench dielectrically isolated complementary bipolar technology is described, which achieves well matched, leakage-free high-speed transistor performance.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International SOI Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1993.344573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The advantages of using full dielectric isolation, in the form of SOI substrates and trench isolation, are well known, namely the reduction of substrate parasitic currents due to high voltage, high temperature or harsh radiation environments. Moreover, high voltage analog bipolar transistors can also benefit from full dielectric isolation in terms of limiting substrate capacitance and providing the means to achieve well matched, densely packed transistors. A high voltage analog SOI/trench dielectrically isolated complementary bipolar technology is described, which achieves well matched, leakage-free high-speed transistor performance.<>