{"title":"A numerical analysis of crack growth and morphology evolution in chip-to-packages nano-interconnections","authors":"S. Koh, R. Tummala, A. Saxena, P. Selvam","doi":"10.1109/ECTC.2008.4550194","DOIUrl":null,"url":null,"abstract":"The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 58th Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2008.4550194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.