High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions

1992 International Technical Digest on Electron Devices Meeting Pub Date : 1900-01-01 DOI:10.1109/IEDM.1992.307503

P. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, S. Sawada

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引用次数: 4

Abstract

A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (>

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采用P/sup +/多晶硅间隔层诱导自排列超浅结的高性能深亚微米埋沟道PMOSFET

提出并开发了一种新的埋沟道PMOSFET结构，该结构通过在主N+多晶硅栅电极旁边形成P+多晶硅侧壁间隔层来实现深亚微米应用。通过使用这种新的器件结构，0.3 μ m PMOSFET的电流可驱动性提高了约40%。电流可驱动性的显著增加可以归因于寄生电阻的降低，这是由于在两个P+多晶硅侧壁间隔层下形成的P型反转层。由于N+多晶硅栅极与P+多晶硅衬垫的功函数不同，P+多晶硅衬垫下的硅表面总是比沟道更倒转。因此，寄生电阻总是远低于通道电阻。此外，这些诱导逆温层作为超浅结(>

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来源期刊

1992 International Technical Digest on Electron Devices Meeting

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