High-speed PNP PIN phototransistors in a 0.18 μm CMOS process

Abstract

In this work we present three speed optimized types of phototransistors built in a standard 180 nm CMOS technology without process modifications. An OPTO ASIC wafer consisting of a p⁺ substrate with a low doped p⁺ epitaxial layer on top of it is used for the implementation. The phototransistors were produced in 40×40 μm² and 100×100 μm² sizes. A gain in responsivity of more than 13 and bandwidths up to 50.7 MHz are achieved. As emitter followers, these phototransistors open the opportunity for application where high-speed photosensitive devices with inherent gain are needed. Possible applications are high speed opto-couplers, optical sensors, image sensors, etc.