On evaluating competing bridge fault models for CMOS ICs

Abstract

Compares the accuracy, speed and applicability to test generation of existing bridge fault modeling solutions. The authors identify some previously undiscussed anomalous circuit behaviors, and describe the extent to which they affect bridge fault simulation and testing. Finally, they present a system for evaluating bridge fault models in a test generation environment, and present an experiment that provides an assessment of how defect coverage can be affected by a generating and checking model.<>