Comparison of key performance metrics in two- and three-dimensional integrated circuits

Abstract

In this paper some key performance metrics in two-dimensional (2-D) and three-dimensional (3-D) integrated circuits (IC) are estimated for scaled technologies from 250-nm to 50-nm technology nodes using a system-level modeling approach. Considering a microprocessor as an example, projections are made for performance metrics such as clock frequency, chip area, interconnect delay and repeater's number for 2-D and 3-D implementation.