On resistance-leakage current trade-off in low-voltage power PMOSFETs

Abstract

The trade-offs that impact minimizing on-resistance while maintaining an acceptable level of leakage current in very low on-resistance buried p-channel MOSFETs are investigated. Gate induced drain leakage (GIDL) current in power PMOSFETs is studied both experimentally and by using numerical simulations. The effect of several carrier generation mechanisms such as band-to-band tunneling, avalanche multiplication and thermal generation on leakage current are also discussed.