The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions

Abstract

Parasitic charge in the passivation layer or at the interface may severely degrade the breakdown capability of high voltage devices. This is attributed to the change of the electric field contours in the presence of the interface charge from an optimal distribution to an unbalanced distribution. A solution to minimise this effect is proposed in this paper. The proposed breakdown termination technique can be used in a wide range of devices such as power MOSFETs, IGBTs or MOS-controlled thyristors and it is especially effective at voltages above 1.2 kV when the n-drift concentration is reduced.