Experimental Characterization and Application of Circuit Architecture Level Single Event Transient Mitigation

Abstract

In this work experimental characterization of process single event transient (SET) performance as a function of circuit node capacitance and drive strength is described. A test structure fabricated on a 130 nm bulk CMOS process is described. Experimental results from ion beam measurements on the structure are also presented. The results can be used early in the design cycle to limit reliability impact due to SETs. An SRAM design example demonstrates how measured SET data can be used to trade off dynamic power dissipation for improved soft error performance without increasing circuit area.