U. Raghunathan, P. Chakraborty, Brian R. Wier, J. Cressler, H. Yasuda, P. Menz
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引用次数: 7
Abstract
We study the accumulated degradation of SiGe HBTs under time-dependent mixed-mode stress using a new physics-based TCAD degradation model that simulates hot carrier generation and propagation to oxide interfaces, resulting in trap formation. We calibrate the avalanche generation and also do a multipoint calibration of damage on the I-V output plane to accurately predict the accumulated stress damage for a single device over multiple bias points. Looking at the region of the output plane dominated by trap formation, we show that accumulation of traps can be path-independent as long as trap availability is not limiting. We demonstrate this with good correlation between simulation and measurement.