A TCAD Framework for Assessing NBTI Impact Under Drain Bias and Self-Heating Effects in Replacement Metal Gate (RMG) p-FinFETs

Abstract

Sentaurus TCAD is enabled to calculate interface trap generation ($\Delta N_{IT}$) during Negative Bias Temperature Instability (NBTI) under drain bias (VD) and self-heating (SH) effects. The setup is calibrated with pure NBTI (VD=0V) experimental data, and is further used to determine the NBTI component during Hot Carrier Degradation (HCD) stress. Such decomposition of NBTI and HCD is demonstrated for multiple fin length (FL) p-FinFETs to model HCD experimental data at different $VG/VD$ stress.