Peripheral circuit design for field programmable MCM systems

Abstract

A field programmable multichip module (MCM) architecture utilizing an array of modified field-programmable gate arrays (FPGAs) is proposed. Interconnections are provided by a fixed wiring network on the MCM, and by programmable interconnection frames on each FPGA. It is shown that full-swing CMOS peripheral circuits are faster than low-swing CMOS circuits. Buffering configurations for the interconnection frame which exploit the MCM performance benefits were selected and optimized. Bidirectional bus implementations using the frame are presented.<>