Novel Cycling-induced Program Disturb of Split Gate Flash Memory

Abstract

Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape