{"title":"Analysis of Material, Design & LER of Advanced BEOL Metal Lines Using Process Modeling","authors":"Daebin Yim, B. Vincent","doi":"10.1109/IITC/MAM57687.2023.10154880","DOIUrl":null,"url":null,"abstract":"We study interconnect metallization options in advanced logic BEOL. Our goal is to choose interconnect materials and process integration options that will reduce RC delay and improve electrical performance. We use process modeling and electrical simulation methods to investigate the impact of metal materials, process variations and LER on the resistance and capacitance of interconnects. Three metal material options are selected, including conventional Cu and Co schemes along with barrier-less Ru. These metal choices are benchmarked to compare and choose the best material and dimensional attributes for advanced Logic BEOL, where traditional scaling may exacerbate RC delay and degrade performance.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC/MAM57687.2023.10154880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We study interconnect metallization options in advanced logic BEOL. Our goal is to choose interconnect materials and process integration options that will reduce RC delay and improve electrical performance. We use process modeling and electrical simulation methods to investigate the impact of metal materials, process variations and LER on the resistance and capacitance of interconnects. Three metal material options are selected, including conventional Cu and Co schemes along with barrier-less Ru. These metal choices are benchmarked to compare and choose the best material and dimensional attributes for advanced Logic BEOL, where traditional scaling may exacerbate RC delay and degrade performance.