Characterization of copper-to-silicon diffusion for the application of 3D packaging with through silicon vias

Abstract

Through silicon vias (TSVs) are one of the major enabling technologies for three-dimensional packaging (3DP). TSVs are usually plugged with plated copper for interconnection. However, the introduction of massive copper in the chip may cause device failure due to the fast diffusion of copper into silicon. In order to reduce this risk, a diffusion barrier layer should be deposited on the sidewall of TSVs between the plated copper and the bulk silicon. In addition, an insulation layer should be deposited as well to prevent short circuit. In this paper, the phenomenon of copper-to-silicon diffusion is characterized. The selected interfacial multilayer structure is Cu/Ti/SiO/sub 2/. Although the ideal specimens should be TSVs with interfacial multilayer deposited on the side wall, it is rather difficult to perform surface analysis on a very small area. Therefore, planar analysis with interfacial multilayer deposited on the top surface of a silicon wafer is performed instead. For comparison purpose, additional cases without insulation layer and/or barrier layer are also investigated. A set of experiments is designed to study the effects of surface roughness and layer thickness. In addition, some samples are subject to high temperature storage for the study of thermal annealing effect.