Resilient SRAM design using BIST-assisted Timing Tracking

Abstract

In this paper, an SRAM design using BIST-assisted timing-tracking (BITT) scheme to improve parametric yield by 76.7% as compared with the traditional timing-tracking method has been presented. This scheme combines reconfigurable delay line, which is tunable by memory BIST, with dummy bitline timing tracking. Consequently, the timing skew due to cell current fluctuations and imbalanced sense amplifiers can both be taken into account so as to provide more flexible timing control for future nanometer technologies.