J. Demarest, B. Austin, J. Arjavac, M. Breton, M. Bergendahl, M. Biedrzycki, C. Boye, B. Cilingiroglu, J. Gaudiello, J. Hager, S. Matham, K. Nguyen, M. Persala, M. Rizzolo, S. Shaar, S. Teehan
{"title":"Transmission Electron Microscopy Sample Preparation By Design Based Recipe Writing in a DBFIB Part 2","authors":"J. Demarest, B. Austin, J. Arjavac, M. Breton, M. Bergendahl, M. Biedrzycki, C. Boye, B. Cilingiroglu, J. Gaudiello, J. Hager, S. Matham, K. Nguyen, M. Persala, M. Rizzolo, S. Shaar, S. Teehan","doi":"10.31399/asm.cp.istfa2019p0470","DOIUrl":null,"url":null,"abstract":"\n Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2019p0470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.