100Gbit/s SiGe Clock and Data Recovery

Abstract

Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.