Yuan Chen, L. Westergard, C. Billman, R. Leon, T. Vo, M. White, M. Mojarradi, E. Kolawa
{"title":"Cryogenic Reliability Impact on Analog Circuits at Extreme Low Temperatures","authors":"Yuan Chen, L. Westergard, C. Billman, R. Leon, T. Vo, M. White, M. Mojarradi, E. Kolawa","doi":"10.1109/RELPHY.2007.369885","DOIUrl":null,"url":null,"abstract":"Cryogenic temperatures have a greater impact on analog circuit reliability than on digital circuit reliability. Analog gain tolerance may provide a more relaxed criterion while the offset voltage criterion has more bias dependence. For a pre-determined analog circuit offset failure criterion and circuit operating temperature profile, either design rules can be generated for the balanced and unbalanced matching transistor pairs in the circuit for certain hot carrier aging life requirement, or the hot carrier aging life time can be estimated for a certain unbalanced matching transistor pairs/chains","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2007.369885","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Cryogenic temperatures have a greater impact on analog circuit reliability than on digital circuit reliability. Analog gain tolerance may provide a more relaxed criterion while the offset voltage criterion has more bias dependence. For a pre-determined analog circuit offset failure criterion and circuit operating temperature profile, either design rules can be generated for the balanced and unbalanced matching transistor pairs in the circuit for certain hot carrier aging life requirement, or the hot carrier aging life time can be estimated for a certain unbalanced matching transistor pairs/chains