New ballasting method for MOS output drivers and power bus clamps

Abstract

New layout styles for MOSFET output drivers and power bus ESD clamps are shown, which provide ballasting with reduced layout area and drain capacitance than the traditional method of using a salicide, blocked drain resistor. Also, an N well ring is placed inside the P+ substrate tie ring of an NFET to increase channel to substrate resistance and improve snap-back conduction uniformity.