LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error

Abstract

We are presenting an automatic approach to produce approximate circuit with formal error guarantees on worst-case relative error (WCRE). The key concept is based on LUTs, SAT -based error evaluation, and property-checking techniques. These approximated circuits are employed to improve scalability and automate the designs for arithmetic circuits. The proposed 8 bit approximate multiplier shows an 83.33 % and 25.3 % decrease in power consumption and delay as w.r.t. exact multiplier. We demonstrated that the use of an approximate multiplier in FIR filter degrades SNR by 1.2 dB.