Investigation of incorporating dielectric pocket (DP) on Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS-DP)

2012 10th IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2012-09-01 DOI:10.1109/SMELEC.2012.6417134

I. Saad, H. M. Zuhir, D. Pogaku, A. R. A. Bakar, N. Bolong, A. M. Khairul, B. Ghosh, R. Ismail, U. Hashim

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引用次数: 9

Abstract

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. Due to the DP layer, improve stability of threshold voltage, VT was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to δp+ triangular potential barrier. Thus, increased amount of gate source voltage for lowering both barriers and allows the electron to move from source to drain. Accordingly, slight different and consistency of VESIMOS-DP sub-threshold value as compared to VESIMOS has revealed to give advantages for incorporating DP layer near the drain end. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect with higher breakdown voltage as compared to without DP layer.

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垂直应变-冲击电离MOSFET (VESIMOS-DP)中加入介电袋(DP)的研究

本文成功研制了具有介电袋的垂直应变硅锗冲击电离MOSFET (VESIMOS-DP)。由于DP层提高了阈值电压的稳定性，在20nm ~ 80nm的不同DP尺寸的VESIMOS-DP器件上发现了VT。这种稳定性是由于源极和漏极之间电荷分担效应的减少。然而，DP层的存在除了引入δp+三角势垒外，还引入了另一个势垒。因此，增加栅极源电压的量，以降低两个势垒，并允许电子从源极移动到漏极。因此，与VESIMOS相比，VESIMOS-DP亚阈值的微小差异和一致性揭示了在漏端附近加入DP层的优势。此外，与没有DP层相比，DP层具有更高的击穿电压，抑制了寄生双极晶体管效应。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)

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