Enabling Cu wire in 3D stack package

Abstract

Over the past two decades, the semiconductor industry has seen a rapid increase in trend for miniaturization of electronic devices. The demand for small and compact size devices has been in every application, be it smartphones, tablets, automotive, industrial, or healthcare equipment. Since 2011, Texas Instruments (TI) has shipped more than 30 million units of its PowerStack packaging technology, a combination of chip stacking and clip bonding that is designed to improve performance and chip densities in power management devices. In PowerStack, TI's NexFET power MOSFETs are stacked on a grounded lead frame. The packaging technology enables heightened integration in a quad flat-pack no-lead (QFN) form factor, cutting down on package area by as much as 50% (compared to side-by-side MOSFETs). However, integration poses multiple packaging manufacturability and reliability challenges, more so for wire bonded devices where complex die to die bonds must be implemented, thus limiting most packaging assembly suppliers to stay with gold (Au) wire. This paper discusses the technical concerns of Cu wire bonding on a three die MCM QFN and the innovative approach to overcome the bonding challenges.