Resolution of poly gate to substrate contact short reliability failures on non-volatile memory

Abstract

Due to continual scaling of CMOS device dimensions, the dielectric spacing between poly gate (PG) and contact to substrate (Con) has been drastically reduced. This reduction in gate to substrate contact spacing has challenged the dielectric breakdown between poly gate and substrate contact. Several studies involving the breakdown of dielectric between gate and substrate contact have been reported in the past. In this paper, we report the elimination of poly gate to substrate contact shorts on 90 nm Non-Volatile Memory technology with the help of process optimizations in pre-metal dielectric stack. This led to a significant improvement in wafer level reliability metric to the tune of ~1.7X.