Design methodology for low power, high-speed CMOS devices utilizing SOI technology

Abstract

We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability.<>