An optimized integration scheme for 0.13 /spl mu/m technology node dual-damascene Cu interconnect

Abstract

From electrical simulations, the best performance dual damascene Cu/FSG integration scheme has been defined to be via first without etching stop layer and with thinnest possible sealing nitride layer. To realize this process, 0.16 /spl mu/m and 0.27 /spl mu/m (local and global interconnect) borderless via chains (100 K) with minimum 0.36 /spl mu/m pitched metal lines (10 cm) were used as test vehicles. Sacrificial layer filled process was then defined with its process window carefully studied. From good electrical results with clearly defined process window, it is concluded that the proposed integration scheme is suitable for sub-0.13 /spl mu/m technology node applications.