Physical understanding and modelling of new hot-carrier degradation effect on PLDMOS transistor

Abstract

Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.