Easy to use evaluation of quality characteristics for a hierarchy of RTL compilers

Abstract

For embedded memories' built-in self-test (BIST) and repair systems gate count and power consumption are among the most critical design constraints. This paper presents an automated method for memory BIST network quality characteristics estimation which is externally seen as “one push button” action. Besides performing area and power-aware memory BIST network design at early stages of SoC design independently from executing step by step the hierarchy of RTL compilers it also excludes a necessity of multiple switching between compiler environments within the hierarchy.